Continuous developments in the fields of analog and digital circuits (such as microprocessors and high speed communications) need efficient electronic components. Compatibility and the integrity of clock signals within the circuits is one of the important requirements. System clock performance that was previously acceptable is now insufficient to support the high clock speeds of today's circuits.
During the engineering phase of validation, jitter characterization of phase-locked loop (PLL) clock is a very important check. A typical set-up consists of Wavecrest or some high-end oscilloscope fed-by the clock under measurement through a probe needle from unpackaged die. The IOs not only add extra jitter to the clock under test (CUT) but also in conjunction with the probe needle capacitance limit the maximum clock frequency that can be brought out for measurement. A divided clock can be used, but division removes high-frequency jitter components. In addition, the cost of jitter measurement equipment limit the ability to replicate results simultaneous by a number of testers, thereby severely reducing test throughput for a given budget. Hence, an on-chip jitter measurement solution can help achieve a high test throughput without the need of special high-speed IO's and expensive test-equipment.
The duty cycle of high speed clocks is very important in certain applications like DDR2 (Double Data Rate 2), where read/write operation is performed on both rising and falling edges of the clock. Measuring duty cycle of high speed clocks is thus very important in these applications. Off chip duty cycle measurement of high speed clocks is not feasible due to speed limitations of IO's and additional distortion caused by intermediate buffers. Hence an on-chip measurement scheme is required to accurately measure duty cycle of high-speed clock signals.
In last few years a number of on-chip jitter measurement techniques have been proposed. The jitter measurement techniques can be widely classified into two categories, analog and digital. Analog technique requires an elaborate calibration step and uses charge pumps, analog to digital convertors, etc.
The commonly proposed digital techniques can be classified into three categories:                1) Programmable delay based techniques: In this approach, the CUT is sampled by its delayed version. This delay is programmable. By controlling this delay to be within a certain fraction smaller and larger than the mean time period, a cumulative distribution function (CDF) curve is obtained and from here RMS jitter is calculated. The resolution of this approach is limited to one buffer delay thereby making it unsuitable for high frequency (>200 MHz) clocks. The meta-stability of flip-flop outputs is another implementation issue.        2) Coherent frequency approach: In this approach a crystal or on-board frequency multiplier is used to generate a clock at a slightly different frequency and the CUT is sampled by this clock. If the two clocks are initially aligned in phase and then allowed to drift then after some time the two clocks will re-align. During each time-period, the CUT will be swept across by the reference clock, the sampling resolution being decided by the differential in the two frequencies. By this technique, sampling resolutions much smaller than a gate delay can be obtained. However, the approach suffers from two drawbacks. First of all, special board or testers are needed to generate the other clock. Secondly, the highest frequency clock on which jitter measurement can be done is limited by the IO's speed limitations since the reference clock has to be nearly as fast as the CUT. Although, this limitation can be overcome by sub-sampling at the cost of removal of high-frequency jitter components, the first drawback limits the generality of the approach.        3) Vernier delay line based (VDL) techniques: In this approach, it's possible to obtain sampling resolutions finer than a buffer delay by using two buffer chains which have slightly different propagation delays. This technique has been used for measuring jitter on data w.r.t to clock. If the data is replaced by CUT and another clean clock is used as reference, then jitter on CUT can be estimated. However, this approach can only work for low-frequency clocks because it is not possible to have another clock which is of as high a frequency as the PLL output clock. Usually this technique is used on divided clocks and hence high-frequency jitter components are eliminated. In addition to this it is argued that a very long VDL (for finer sampling resolution) will suffer from buffer mismatch.        
FIG. 1 illustrates a conventional time interval measuring device 100 using a component-invariant VDL. A single-stage VDL structure 100 includes a data-triggered oscillator circuit 101, a clock-triggered oscillator circuit 102, and a D-latch 103. Data-triggered oscillator circuit 101 feeds a first signal into the data line input of D-latch 103. Clock-triggered oscillator circuit 102 feeds a second signal into the clock input of the same respective D-latch 103. The output of the D-latch 103 is passed to a counter. Data-triggered oscillator 101 is triggered by a data signal while the clock-triggered oscillator 102 is triggered by a clock signal. In this technique, two oscillators with slightly different oscillation frequencies (much smaller than the frequency of CUT) are designed. The slower oscillator starts oscillating at the first rising edge of the clock and the fast oscillator starts oscillating after a fixed delay provided after the first rising edge. In each oscillation cycle, time difference between the two clocks decreases byTD=TS−TF,where                TS=Time period of slow oscillator        TF=Time period of fast Oscillator        TD=sampling resolution.        
If the number of cycles required by the fast oscillator to overtake the slow oscillator is N, then the measured time period=N*TD. In this way many measurements are made and again a CDF is plotted and from there the RMS jitter is estimated. The problems with this approach are:                A well-defined delay is required. An elaborate calibration step is also required for estimating TD.        For a small sampling resolution and a large Time-Period, the N above will be large. The jitter in the vernier oscillators will accumulate for N-periods and cause a very large measurement inaccuracy as this inaccuracy will directly add to the jitter estimate in the CUT.        For high-frequency clocks, the accumulated jitter in the oscillators can become larger or comparable to the jitter under measurement. Hence this approach cannot be used reliably for high-frequency clocks.        The test-time can become extremely large, because one sample is acquired per oscillation cycle and the oscillation frequency is typically much smaller than the frequency of CUT.        
The measurement of duty-cycle of a clock signal is an important part of most on-chip phase-locked loop (PLL) built-in-self-test (BIST) solutions. Duty cycle is an important PLL clock specification for DDR2 kind of applications and its measurement is a vital part of any PLL BIST solution. The conventional approaches for measuring and correcting duty cycle can be categorized broadly into analog, digital and mixed-signal. Purely analog duty cycle corrector (DCC) circuits like the one proposed by Toru Ogawa, Kenji Taniguchi in ISCAS-2002, Vol. 4, entitled A 50% Duty-Cycle Correction Circuit for PLL Output, consist of a voltage controlled oscillator (VCO), operational amplifiers (OPAMP), phase detectors and frequency filters that makes the design extremely resource-hungry. These circuits are obviously not a good choice when die area is the most important constraint. Moreover, in a typical digital BIST environment, purely analog approaches can not be used. Further all the conventional techniques for jitter and duty-cycle measurement require another clock for calibration and special circuit components.
Therefore, there is a need of a system and method for on-chip jitter and duty cycle measurement using a single clock signal.